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MACROS05.MAC
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****************************************************************************
* macros05.mac 1.0
* -------------------------------------------------------------
* Module Name: MACROS05 - M6805 Macros
* -------------------------------------------------------------
*
* Description:
* This file contains macros and subroutines to support pseudo-registers
* on the 6805 that simulate registers and addressing modes available on
* the 68HC11. It is suitable for "black box" operation, i.e., the
* macros may be used without knowledge of how they work. A list of the
* supported macros follows. Consult the individual macro headers for
* usage details and see the "Notes" below.
*
* LDD Load DREG
* STD Store DREG
* ADDD Add DREG
* SUBD Add DREG
* CPD Compare DREG
* LDAXY Load A via 16-bit pseudo-register (XREG or YREG)
* STAXY Store A via 16-bit pseudo-register (XREG or YREG)
* LDXR Load XREG
* STXR Store XREG
* INCXR Increment XREG
* DECXR Decrement XREG
* CPXR Compare XREG
* LDYR Load YREG
* STYR Store YREG
* INCYR Increment YREG
* DECYR Decrement YREG
* CPYR Compare YREG
* DEC.B Decrement byte
* DEC.W Decrement word
* INC.B Increment byte
* INC.W Increment word
* MOV.B Move byte
* MOV.W Move word
* MOVE Move block of memory
*
* General Information:
* The following pseudo-registers are supported.
* DREG = pseudo 16-bit accumulator (A,X registers, A is MS half)
* XREG = pseudo 16-bit index register
* YREG = pseudo 16-bit index register
*
* The following terms are used.
* # = specifies immediate addressing mode
* <address> = address/value operand (absolute or immediate)
* <offset> = unsigned 16-bit offset for indexed addressing
*
* Notes:
* 1. Motorola reserves the right to make changes to this file.
* Although this file has been carefully reviewed and is believed
* to be reliable, Motorola does not assume any liability arising
* out of its use. This code may be freely used and/or modified at
* no cost or obligation by the user.
* 2. This file was made for use with the Motorola Development Systems
* MC6805 Portable Assembler/Linker for MS-DOS, known as PASM05 and
* PLD, as released on 82HCVBASM B* and 82HCVBLNK B*. Consult the
* PASM and PLD reference manuals, part numbers M68HASM/D1 and
* M68HLINK/D1, for more details.
* 3. These macros were made for ABSOLUTE assemblies only, i.e., for
* use with ORG directives. While most of the macro concepts will
* work in relocatable assemblies (BSCT, DSCT, PSCT, ASCT, XDEF,
* and XREF), errors will be generated because PASM limits the use
* of external symbols in expressions and because the value of an
* expression must be known at assembly time for IFxx directives to
* assemble the proper code. The first restriction is a result of
* limitations in the COFF object file format. If it is desired to
* have these macros work with relocatable assemblies, modifica-
* tions similar to below should be made, but be forewarned of the
* increased inefficiencies in size and speed. Consider the
* following code to change the LDD macro so that an XREF parameter,
* \1, can be loaded as an immediate value.
* LDA \.8
* LDX \.8+1
* BRA \.9
* \.8 FDB \1
* \.9 EQU *
* 4. In order to efficiently support both LOAD and STORE operations
* for the pseudo 16-bit index registers, there are actually two
* such "registers", i.e., one for LOAD and one for STORE as
* defined below. These routines maintain both "registers" with
* the same value, and so the programmer may think of them as one
* register.
* XREG1$ = 16-bit XREG for LOAD operations
* XREG2$ = 16-bit XREG for STORE operations
* YREG1$ = 16-bit YREG for LOAD operations
* YREG2$ = 16-bit YREG for STORE operations
* 5. These macros can be used to create in-line code (speed
* efficient) or they be placed in a subroutine (byte efficient).
* 6. Instruction modified code is used here and is denoted by use
* of the unique string "0-0" (RAM subroutines).
* 7. Some macros use temporary storage locations (TEMPA$, TESTA$,
* etc.), so these macros should not be used in any interrupt
* routine in order to avoid corrupted values!
* 8. The user must ensure that the code is appropriately placed in
* the target M6805's memory map, i.e., the RAM subroutines MUST
* be located in RAM but must not overlap the stack area ($00C0-
* 00FF) unless it can be GUARANTEED there is no conflict! See
* LO$MEM below to set low memory data storage area!
* 9. To use this file, either use an INCLUDE statement or just
* merge this file into your source code file. Consult your
* assembler's user's manual for the details specific to your
* situation. When using a ROM controlled system, the MOVE
* macro should be used to copy the RAM subroutines from ROM to
* RAM (see the comments after where RAMSBR$ is defined below
* and note the INCLUDE statement for the RAMSBR.INI file).
* Reference the code segment example below for usage ideas
* (shown in PASM05 for MS-DOS syntax).
*
* ORG $50
* TOTAL RMB 2
* RTABLE RMB 5
* INCLUDE MACROS05.MAC
*
* ORG $400
* RESET RSP
* MOVE #,.RAMSBR$,#,RAMSBR$,#,RAMSZ$ Init ram.
* START MOV.W #,0,TOTAL
* LDD COST
* ADDD #,1000
* SUBD #,ADJUST
* ADDD TOTAL
* STDD TOTAL
* CPD #,1500
* BEQ MATCH
* *
* LDXR #,0
* LDYR #,0
* LOOP LDAXY TABLE,XREG
* STAXY RTABLE,YREG
* INCXR
* INCYR
* CPY #,5
* BNE LOOP
* .
* .
* INCLUDE RAMSBR.INI
* TABLE FCB 1,2,3,4,5
* ADJUST FDB 150
* COST FDB 859
* .
* .
* END
*
* 10. To assemble, use the following sample invocation lines:
* pasm05 -eq -l filename.lst filename.s (debug= expanded)
* or
* pasm05 -bf -l filename.lst filename.s (black box)
* 11. Notations used by PASM05 are as follows:
* OPERATORS: Special two character operators used are...
* 1. Logical AND !.
* 2. Shift Right (0 fill on left) !>
* MACROS: Special notations used are...
* 1. Parameters are positionally named using \0,
* \1, \2, etc.
* 2. Labels within macros are designated via \.a,
* where "a" is an alphanumeric character. The
* assembler generates a unique label to avoid
* multiply defined label problems.
* 12. Some macros access 16-bit values as LS byte then MS byte in order
* to be more efficient for condition code (CC) setting. This is
* the reverse order that the 68HC11 would access the two byte
* halves. This difference would only be a concern in accessing
* hardware registers, as normal RAM makes no difference. Those
* macros with this difference have an entry in their Notes section.
* 13. The latest version of this file is maintained on the Motorola
* FREEWARE Bulletin Board, 512/891-FREE (512/891-3733). It operates
* continuously (except for maintenance) at 1200-2400 baud, 8 bits,
* no parity. Sample test files for PASM05 are also included.
* Download the archive file, MACROS05.ARC, to get all the files.
*
**************************************************************************
* REVISION HISTORY (add new changes to top):
*
* 05/16/90 P.S. Gilmour
* 1. Created for Application Note AN1055.
**************************************************************************
LO$MEM EQU $00C0-7 Low memory ($0000-00FF) storage (7 bytes)
OPT NOL
**************************************************************************
* LDD = load DREG
* LDD [#,]<address>
*
* Examples:
* 1. "LDD #,START" puts the value of symbol 'START' into
* the DREG (=A,X).
* 2. "LDD START" puts the contents of location 'START'
* and 'START'+1 into the DREG (=A,X).
*
* Register Usage:
* A,X = loaded with new value (DREG).
* CC = reflects MS half (=A).
* All other registers preserved.
*
* Notes:
* 1. Byte access order is LS, then MS (reversed from 68HC11).
*
LDD MACR
IFEQ NARG-1
LDX (\0)+1
LDA (\0)
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
IFEQ (\1)!.$FF
CLRX
ENDC
IFNE (\1)!.$FF
LDX #(\1)!.$FF
ENDC
IFEQ (\1)!>8
CLRA
ENDC
IFNE (\1)!>8
LDA #(\1)!>8
ENDC
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* STD = store DREG
* STD <address>
*
* Examples:
* 1. "STD START" stores the DREG (=A,X) into locations
* 'START' and 'START'+1.
*
* Register Usage:
* CC = reflects MS half (=A).
* All other registers preserved.
*
* Notes:
* 1. Byte access order is LS, then MS (reversed from 68HC11).
*
STD MACR
STX (\0)+1
STA (\0)
ENDM
**************************************************************************
* ADDD = add DREG
* ADDD [#,]<address>
*
* Examples:
* 1. "ADDD #,START" adds the value of symbol 'START' to the
* DREG (=A,X).
* 2. "ADDD START" adds the contents of location 'START'
* and 'START'+1 to the DREG (=A,X).
*
* Register Usage:
* A,X = contains new value (DREG).
* CC = reflects MS half (=A).
* All other registers preserved.
*
ADDD MACR
IFEQ NARG-1
STA TEMPA$
TXA
ADD (\0)+1
TAX
LDA TEMPA$
ADC (\0)
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
STA TEMPA$
TXA
ADD #(\1)!.$FF
TAX
LDA TEMPA$
ADC #(\1)!>8
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* SUBD = add DREG
* SUBD [#,]<address>
*
* Examples:
* 1. "SUBD #,START" subtracts the value of symbol 'START' from
* the DREG (=A,X).
* 2. "SUBD START" subtracts the contents of location 'START'
* and 'START'+1 from the DREG (=A,X).
*
* Register Usage:
* A,X = contains new value (DREG).
* CC = reflects MS half (=A).
* All other registers preserved.
*
SUBD MACR
IFEQ NARG-1
STA TEMPA$
TXA
SUB (\0)+1
TAX
LDA TEMPA$
SBC (\0)
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
STA TEMPA$
TXA
SUB #(\1)!.$FF
TAX
LDA TEMPA$
SBC #(\1)!>8
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* CPD = compare DREG
* CPD [#,]<address>
*
* Examples:
* 1. "CPD #,BLOCKSZ" compares the value of symbol 'BLOCKSZ'
* with the DREG (=A,X).
* 2. "CPD START" compares the contents of location
* 'START' and 'START'+1 with the DREG.
*
* Register Usage:
* CC = reflects DREG comparison (Z-bit only).
* All other registers preserved.
*
CPD MACR
IFEQ NARG-1
CPX (\0)+1
BNE \.0
CMP (\0)
\.0 EQU *
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
IFEQ (\1)!.$FF
TSTX
ENDC
IFNE (\1)!.$FF
CPX #(\1)!.$FF
ENDC
BNE \.0
IFEQ (\1)!>8
TSTA
ENDC
IFNE (\1)!>8
CMP #(\1)!>8
ENDC
\.0 EQU *
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* LDAXY = load A via 16-bit pseudo-register (XREG or YREG)
* LDAXY <offset>,XREG
* LDAXY <offset>,YREG
*
* Examples:
* 1. "LDAXY 0,XREG" loads the contents of the memory location
* specified by XREG+0 into the A accumulator.
* 2. "LDAXY ,XREG" loads the contents of the memory location
* specified by XREG+0 into the accumulator.
* 3. "LDAXY TBL,XREG" loads the contents of the memory location
* specified by XREG+'TBL' into the A accum-
* ulator.
* 4. Above examples can be repeated with substituting YREG for XREG.
*
* Register Usage:
* A = loaded with new value.
* DREG= destroyed.
* CC = reflects value loaded.
* All other registers preserved.
*
LDAXY MACR
IFNC '\1','XREG'
IFNC '\1','YREG'
FAIL Macro syntax error detected!
MEXIT
ENDC
ENDC
IFC '\0',''
JSR LDA\1 Default offset= 0
MEXIT
ENDC
IFNC '\0',''
IFEQ \0
JSR LDA\1 Offset= 0
MEXIT
ENDC
IFNE \0
LDA \11$+1 Set nREG= offset + nREG
ADD #(\0)!.$FF
STA \11$+1
LDA \11$
ADC #(\0)!>8
STA \11$
JSR LDA\1 Offset= 0
STA TEMPA$
LDA \12$ Restore nREG
STA \11$
LDA \12$+1
STA \11$+1
LDA TEMPA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* STAXY = store A via 16-bit pseudo-register (XREG or YREG)
* STAXY <offset>,XREG
* STAXY <offset>,YREG
*
* Examples:
* 1. "STAXY 0,XREG" stores the accumulator (=A) into the memory
* location specified by XREG+0.
* 2. "STAXY ,XREG" stores the accumulator (=A) into the memory
* location specified by XREG+0.
* 3. "STAXY TBL,XREG" stores the accumulator (=A) into the memory
* specified by XREG+'TBL'.
* 4. Above examples can be repeated with substituting YREG for XREG.
*
* Register Usage:
* CC = reflects value stored.
* All other registers preserved.
*
STAXY MACR
IFNC '\1','XREG'
IFNC '\1','YREG'
FAIL Macro syntax error detected!
MEXIT
ENDC
ENDC
IFC '\0',''
JSR STA\1 Default offset= 0
MEXIT
ENDC
IFNC '\0',''
IFEQ \0
JSR STA\1 Offset= 0
MEXIT
ENDC
IFNE \0
STA TEMPA$
LDA \12$+1 Set nREG= offset + nREG
ADD #(\0)!.$FF
STA \12$+1
LDA \12$
ADC #(\0)!>8
STA \12$
LDA TEMPA$
JSR STA\1 Offset= 0
LDA \11$ Restore nREG
STA \12$
LDA \11$+1
STA \12$+1
LDA TEMPA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* LDXR = load XREG
* LDXR [#,]<address>
*
* Examples:
* 1. "LDXR #,START" puts the value of symbol 'START' into the
* XREG.
* 2. "LDXR START" puts the contents of location 'START' and
* 'START'+1 into the XREG.
*
* Register Usage:
* CC = reflects MS half (=A).
* All other registers preserved.
*
* Notes:
* 1. Byte access order is LS, then MS (reversed from 68HC11).
*
LDXR MACR
IFEQ NARG-1
STA TEMPA$
LDA (\0)+1
STA XREG1$+1
STA XREG2$+1
LDA (\0)
STA XREG1$
STA XREG2$
IFEQ XREG1$!.$FF00
LDA TEMPA$
TST XREG1$
ENDC
IFNE XREG1$!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
ENDC
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
IFEQ XREG1$!.$FF00 ! XREG in low memory?
IFEQ \1 ! #0 value?
CLR XREG1$+1
CLR XREG2$+1
CLR XREG1$
CLR XREG2$
MEXIT
ENDC
IFNE \1 ! not #0 value?
STA TEMPA$
IFEQ (\1)!.$FF
CLR XREG1$+1
CLR XREG2$+1
ENDC
IFNE (\1)!.$FF
LDA #(\1)!.$FF
STA XREG1$+1
STA XREG2$+1
ENDC
IFEQ (\1)!>8
CLR XREG1$
CLR XREG2$
ENDC
IFNE (\1)!>8
LDA #(\1)!>8
STA XREG1$
STA XREG2$
ENDC
LDA TEMPA$
TST XREG1$
MEXIT
ENDC
ENDC
IFNE XREG1$!.$FF00 ! XREG in high memory?
IFEQ \1 ! #0 value?
STA TEMPA$
CLRA
STA XREG1$+1
STA XREG2$+1
STA XREG1$
STA XREG2$
CLR TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFNE \1 ! not #0 value?
STA TEMPA$
IFEQ (\1)!.$FF
CLRA
ENDC
IFNE (\1)!.$FF
LDA #(\1)!.$FF
ENDC
STA XREG1$+1
STA XREG2$+1
IFEQ (\1)!>8
CLRA
ENDC
IFNE (\1)!>8
LDA #(\1)!>8
ENDC
STA XREG1$
STA XREG2$
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* STXR = store XREG
* STXR <address>
*
* Examples:
* 1. "STXR START" stores the XREG into locations 'START' and
* 'START'+1.
*
* Register Usage:
* CC = reflects MS half (=A).
* All other registers preserved.
*
* Notes:
* 1. Byte access order is LS, then MS (reversed from 68HC11).
*
STXR MACR
STA TEMPA$
LDA XREG1$+1
STA (\0)+1
LDA XREG1$
STA (\0)
IFEQ XREG1$!.$FF00
LDA TEMPA$
TST XREG1$
ENDC
IFNE XREG1$!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
ENDC
ENDM
**************************************************************************
* INCXR = increment XREG
* INCXR [[#,]<address>]
*
* Examples:
* 1. "INCXR" adds one (1) to the XREG.
* 2. "INCXR #,START" adds the value of symbol 'START' to the
* XREG.
* 3. "INCXR START" adds the contents of location 'START' and
* 'START'+1 to the XREG.
* 4. "INCXR ! comment" adds one (1) to the XREG (comment present!).
*
* Register Usage:
* CC = reflects value incremented (Z-bit only).
* All other registers preserved.
*
* Notes:
* 1. Explicit comment character (!) MUST be used when comment field is
* present to prevent confusion with parameters!
* 2. Assumes XREG1$ = XREG2$.
* 3. When parameters are present, this macro becomes "ADD to XREG".
*
INCXR MACR
IFEQ NARG
IFEQ XREG1$!.$FF00
INC XREG1$+1
INC XREG2$+1
BNE \.0
INC XREG1$
INC XREG2$
\.0 EQU *
MEXIT
ENDC
IFNE XREG1$!.$FF00
STA TEMPA$
LDA XREG1$+1
ADD #1
STA XREG1$+1
STA XREG2$+1
LDA XREG1$
ADC #0
STA XREG1$
STA XREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
IFEQ NARG-1
STA TEMPA$
LDA XREG1$+1
ADD (\0)+1
STA XREG1$+1
STA XREG2$+1
LDA XREG1$
ADC \0
STA XREG1$
STA XREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
STA TEMPA$
LDA XREG1$+1
ADD #(\1)!.$FF
STA XREG1$+1
STA XREG2$+1
LDA XREG1$
ADC #(\1)!>8
STA XREG1$
STA XREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* DECXR = decrement XREG
* DECXR [[#,]<address>]
*
* Examples:
* 1. "DECXR" subtracts one (1) from the XREG.
* 2. "DECXR #,START" subtracts the value of symbol 'START' from
* the XREG.
* 3. "DECXR START" subtracts the contents of location 'START'
* and 'START'+1 from the XREG.
* 4. "DECXR ! comment" subtracts one from the XREG (comment present!).
*
* Register Usage:
* CC = reflects value decremented (Z-bit only).
* All other registers preserved.
*
* Notes:
* 1. Explicit comment character (!) MUST be used when comment field is
* present!
* 2. Assumes XREG1$ = XREG2$.
* 3. When parameters are present, this macro becomes "SUBTRACT from XREG".
*
DECXR MACR
IFEQ NARG
STA TEMPA$
LDA XREG1$+1
SUB #1
STA XREG1$+1
STA XREG2$+1
LDA XREG1$
SBC #0
STA XREG1$
STA XREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-1
STA TEMPA$
LDA XREG1$+1
SUB (\0)+1
STA XREG1$+1
STA XREG2$+1
LDA XREG1$
SBC \0
STA XREG1$
STA XREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
STA TEMPA$
LDA XREG1$+1
SUB #(\1)!.$FF
STA XREG1$+1
STA XREG2$+1
LDA XREG1$
SBC #(\1)!>8
STA XREG1$
STA XREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* CPXR = compare XREG
* CPXR [#,]<address>
*
* Examples:
* 1. "CPXR #,BLOCKSZ" compares the value of symbol 'BLOCKSZ'
* with the XREG.
* 2. "CPXR START" compares the contents of location
* 'START' and 'START'+1 with the XREG.
*
* Register Usage:
* CC = reflects XREG comparison (Z-bit only).
* All other registers preserved.
*
CPXR MACR
IFEQ NARG-1
STA TEMPA$
BSET 0,TESTA$ Preset for .NE. condition!
LDA XREG1$+1
CMP (\0)+1
BNE \.0 Branch if LS half is .NE.
LDA XREG1$
CMP (\0)
BNE \.0 Branch if MS half is .NE.
CLR TESTA$ Set for .EQ. condition!
\.0 LDA TEMPA$
TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
IFEQ \1
IFEQ XREG1$!.$FF00
TST XREG1$+1
BNE \.0 Branch if LS half is .NE.
TST XREG1$
\.0 EQU *
MEXIT
ENDC
IFNE XREG1$!.$FF00
STA TEMPA$
BSET 0,TESTA$ Preset for .NE. condition!
LDA XREG1$+1
BNE \.0 Branch if MS half is .NE.
LDA XREG1$
BNE \.0 Branch if MS half is .NE.
CLR TESTA$ Set for .EQ. condition!
\.0 LDA TEMPA$
TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
MEXIT
ENDC
ENDC
STA TEMPA$
BSET 0,TESTA$ Preset for .NE. condition!
LDA XREG1$+1
IFNE (\1)!.$FF
CMP #(\1)!.$FF
ENDC
BNE \.0 Branch if LS half is .NE.
LDA XREG1$
IFNE (\1)!>8
CMP #(\1)!>8
ENDC
BNE \.0 Branch if MS half is .NE.
CLR TESTA$ Set for .EQ. condition!
\.0 LDA TEMPA$
TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* LDYR = load YREG
* LDYR [#,]<address>
*
* Examples:
* 1. "LDYR #,START" puts the value of symbol 'START' into the
* YREG.
* 2. "LDYR START" puts the contents of location 'START' and
* 'START'+1 into the YREG.
*
* Register Usage:
* CC = reflects MS half.
* All other registers preserved.
*
LDYR MACR
IFEQ NARG-1
STA TEMPA$
LDA (\0)
STA YREG1$
STA YREG2$
LDA (\0)+1
STA YREG1$+1
STA YREG2$+1
IFEQ YREG1$!.$FF00
LDA TEMPA$
TST YREG1$
ENDC
IFNE YREG1$!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
ENDC
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
IFEQ YREG1$!.$FF00 ! YREG in low memory?
IFEQ \1 ! #0 value?
CLR YREG1$+1
CLR YREG2$+1
CLR YREG1$
CLR YREG2$
MEXIT
ENDC
IFNE \1 ! not #0 value?
STA TEMPA$
IFEQ (\1)!.$FF
CLR YREG1$+1
CLR YREG2$+1
ENDC
IFNE (\1)!.$FF
LDA #(\1)!.$FF
STA YREG1$+1
STA YREG2$+1
ENDC
IFEQ (\1)!>8
CLR YREG1$
CLR YREG2$
ENDC
IFNE (\1)!>8
LDA #(\1)!>8
STA YREG1$
STA YREG2$
ENDC
LDA TEMPA$
TST YREG1$
MEXIT
ENDC
ENDC
IFNE YREG1$!.$FF00 ! YREG in high memory?
IFEQ \1 ! #0 value?
STA TEMPA$
CLRA
STA YREG1$+1
STA YREG2$+1
STA YREG1$
STA YREG2$
CLR TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFNE \1 ! not #0 value?
STA TEMPA$
IFEQ (\1)!.$FF
CLRA
ENDC
IFNE (\1)!.$FF
LDA #(\1)!.$FF
ENDC
STA YREG1$+1
STA YREG2$+1
IFEQ (\1)!>8
CLRA
ENDC
IFNE (\1)!>8
LDA #(\1)!>8
ENDC
STA YREG1$
STA YREG2$
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* STYR = store YREG
* STYR <address>
*
* Examples:
* 1. "STYR START" stores the YREG into locations 'START' and
* 'START'+1.
*
* Register Usage:
* CC = reflects MS half.
* All other registers preserved.
*
STYR MACR
STA TEMPA$
LDA YREG1$
STA (\0)
LDA YREG1$+1
STA (\0)+1
IFEQ YREG1$!.$FF00
LDA TEMPA$
TST YREG1$
ENDC
IFNE YREG1$!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
ENDC
ENDM
**************************************************************************
* INCYR = increment YREG
* INCYR [[#,]<value>]
*
* Examples:
* 1. "INCYR" adds one (1) to the YREG.
* 2. "INCYR #,START" adds the value of symbol 'START' to the
* YREG.
* 3. "INCYR START" adds the contents of location 'START' and
* 'START'+1 to the YREG.
* 4. "INCYR ! comment" adds one (1) to the YREG (comment present!).
*
* Register Usage:
* CC = reflects value incremented (Z-bit only).
* All other registers preserved.
*
* Notes:
* 1. Explicit comment character (!) MUST be used when comment field is
* present!
* 2. Assumes YREG1$ = YREG2$.
* 3. When parameters are present, this macro becomes "ADD to YREG".
*
INCYR MACR
IFEQ NARG
IFEQ YREG1$!.$FF00
INC YREG1$+1
INC YREG2$+1
BNE \.0
INC YREG1$
INC YREG2$
\.0 EQU *
MEXIT
ENDC
IFNE YREG1$!.$FF00
STA TEMPA$
LDA YREG1$+1
ADD #1
STA YREG1$+1
STA YREG2$+1
LDA YREG1$
ADC #0
STA YREG1$
STA YREG2$
ORA YREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
IFEQ NARG-1
STA TEMPA$
LDA YREG1$+1
ADD (\0)+1
STA YREG1$+1
STA YREG2$+1
LDA YREG1$
ADC \0
STA YREG1$
STA YREG2$
ORA YREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
STA TEMPA$
LDA YREG1$+1
ADD #(\1)!.$FF
STA YREG1$+1
STA YREG2$+1
LDA YREG1$
ADC #(\1)!>8
STA YREG1$
STA YREG2$
ORA XREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* DECYR = decrement YREG
* DECYR [[#,]<value>]
*
* Examples:
* 1. "DECYR" subtracts one (1) from the YREG.
* 2. "DECYR #,START" subtracts the value of symbol 'START' from
* the YREG.
* 3. "DECYR START" subtracts the contents of location 'START'
* and 'START'+1 from the YREG.
* 4. "DECYR ! comment" subtracts one from the YREG (comment present!).
*
* Register Usage:
* CC = reflects value decremented (Z-bit only).
* All other registers preserved.
*
* Notes:
* 1. Explicit comment character (!) MUST be used when comment field is
* present!
* 2. Assumes YREG1$ = YREG2$.
* 3. When parameters are present, this macro becomes "SUBTRACT from YREG".
*
DECYR MACR
IFEQ NARG
STA TEMPA$
LDA YREG1$+1
SUB #1
STA YREG1$+1
STA YREG2$+1
LDA YREG1$
SBC #0
STA YREG1$
STA YREG2$
ORA YREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-1
STA TEMPA$
LDA YREG1$+1
SUB (\0)+1
STA YREG1$+1
STA YREG2$+1
LDA YREG1$
SBC \0
STA YREG1$
STA YREG2$
ORA YREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
STA TEMPA$
LDA YREG1$+1
SUB #(\1)!.$FF
STA YREG1$+1
STA YREG2$+1
LDA YREG1$
SBC #(\1)!>8
STA YREG1$
STA YREG2$
ORA YREG1$+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* CPYR = compare YREG
* CPYR [#,]<address>
*
* Examples:
* 1. "CPYR #,BLOCKSZ" compares the value of symbol 'BLOCKSZ'
* with the YREG.
* 2. "CPYR START" compares the contents of location
* 'START' and 'START'+1 with the YREG.
*
* Register Usage:
* CC = reflects YREG comparison (Z-bit only).
* All other registers preserved.
*
CPYR MACR
IFEQ NARG-1
STA TEMPA$
BSET 0,TESTA$ Preset for .NE. condition!
LDA YREG1$+1
CMP (\0)+1
BNE \.0 Branch if LS half is .NE.
LDA YREG1$
CMP (\0)
BNE \.0 Branch if MS half is .NE.
CLR TESTA$ Set for .EQ. condition!
\.0 LDA TEMPA$
TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
MEXIT
ENDC
IFEQ NARG-2
IFC '\0','#'
IFEQ \1
IFEQ YREG1$!.$FF00
TST YREG1$+1
BNE \.0 Branch if LS half is .NE.
TST YREG1$
\.0 EQU *
MEXIT
ENDC
IFNE YREG1$!.$FF00
STA TEMPA$
BSET 0,TESTA$ Preset for .NE. condition!
LDA YREG1$+1
BNE \.0 Branch if MS half is .NE.
LDA YREG1$
BNE \.0 Branch if MS half is .NE.
CLR TESTA$ Set for .EQ. condition!
\.0 LDA TEMPA$
TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
MEXIT
ENDC
ENDC
STA TEMPA$
BSET 0,TESTA$ Preset for .NE. condition!
LDA YREG1$+1
IFNE (\1)!.$FF
CMP #(\1)!.$FF
ENDC
BNE \.0 Branch if LS half is .NE.
LDA YREG1$
IFNE (\1)!>8
CMP #(\1)!>8
ENDC
BNE \.0 Branch if MS half is .NE.
CLR TESTA$ Set for .EQ. condition!
\.0 LDA TEMPA$
TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* DEC.B = decrement byte
* DEC.B [[#,]<value>,]<address>
*
* where:
* <value> = value to decrement the contents of the <address>
* location by; immediate ("#," present) or absolute
* addressing ("#," not present). If only <address> is
* specified, a default immediate value of one is used.
*
* Examples:
* 1. "DEC.B START" subtracts one from the contents of
* location 'START'.
* 2. "DEC.B #,5,START" subtracts five from the contents of
* location 'START'.
* 3. "DEC.B CNT,START" subtracts the contents of location 'CNT'
* from the contents of location 'START'.
*
* Register Usage:
* CC = reflects value decremented (N and Z-bits).
* All other registers preserved.
*
* Notes:
* 1. <address> may be direct or extended!
* 2. This macro essentially performs a "SUB n" function.
*
DEC.B MACR
IFEQ NARG-1
IFEQ (\0)!.$FF00
DEC \0
MEXIT
ENDC
STA TEMPA$
LDA \0
SUB #1
STA \0
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
STA TEMPA$
LDA \1
SUB \0
STA \1
IFEQ (\1)!.$FF00
LDA TEMPA$
TST \1
MEXIT
ENDC
IFNE (\1)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
IFEQ NARG-3
IFC '\0','#'
STA TEMPA$
LDA \2
SUB #\1
STA \2
IFEQ (\2)!.$FF00
LDA TEMPA$
TST \2
MEXIT
ENDC
IFNE (\2)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* DEC.W = decrement word
* DEC.W [[#,]<value>,]<address>
*
* where:
* <value> = value to decrement the contents of the <address> and
* <address>+1 locations by; immediate ("#," present) or
* absolute addressing ("#," not present). If only
* <address> is specified, a default immediate value of
* one is used.
*
* Examples:
* 1. "DEC.W START" subtracts one from the contents of loca-
* tions 'START' and 'START'+1.
* 2. "DEC.W CNT,START" subtracts the contents of locations 'CNT'
* and 'CNT'+1 from the contents of locations
* 'START' and 'START'+1.
* 3. "DEC.W #,5,START" subtracts five from the contents of loca-
* tions 'START' and 'START'+1.
*
* Register Usage:
* CC = reflects value incremented (Z-bit only).
* All other registers preserved.
*
* Notes:
* 1. <address> may be direct or extended!
* 2. This macro essentially performs a "SUB n" function.
*
DEC.W MACR
IFEQ NARG-1
STA TEMPA$
LDA (\0)+1
SUB #1
STA (\0)+1
LDA \0
SBC #0
STA \0
ORA (\0)+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
STA TEMPA$
LDA (\1)+1
SUB (\0)+1
STA (\1)+1
LDA \1
SBC \0
STA \1
ORA (\1)+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-3
IFC '\0','#'
STA TEMPA$
LDA (\2)+1
SUB #(\1)!.$FF
STA (\2)+1
LDA \2
SBC #(\1)!>8
STA \2
ORA (\2)+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* INC.B = increment byte
* INC.B [[#,]<value>,]<address>
*
* where:
* <value> = value to decrement the contents of the <address>
* location by; immediate ("#," present) or absolute
* addressing ("#," not present). If only <address> is
* specified, a default immediate value of one is used.
*
* Examples:
* 1. "INC.B START" adds one to the contents of location
* 'START'.
* 2. "INC.B #,5,START" adds five to the contents of location
* 'START'.
* 3. "INC.B CNT,START" adds the contents of location 'CNT' to
* the contents of location 'START'.
*
* Register Usage:
* CC = reflects value incremented (N and Z-bits).
* All other registers preserved.
*
* Notes:
* 1. <address> may be direct or extended!
* 2. This macro essentially performs an "ADD n" function.
*
INC.B MACR
IFEQ NARG-1
IFEQ (\0)!.$FF00
INC \0
MEXIT
ENDC
STA TEMPA$
LDA \0
ADD #1
STA \0
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-2
STA TEMPA$
LDA \1
ADD \0
STA \1
IFEQ (\1)!.$FF00
LDA TEMPA$
TST \1
MEXIT
ENDC
IFNE (\1)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
IFEQ NARG-3
IFC '\0','#'
STA TEMPA$
LDA \2
ADD #\1
STA \2
IFEQ (\2)!.$FF00
LDA TEMPA$
TST \2
MEXIT
ENDC
IFNE (\2)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* INC.W = increment word
* INC.W [[#,]<value>,]<address>
*
* where:
* <value> = value to increment the contents of the <address> and
* <address>+1 locations by; immediate ("#," present)
* or absolute addressing ("#," not present). If only
* <address> is specified, a default immediate value of
* one is used.
*
* Examples:
* 1. "INC.W START" adds one to the contents of locations
* 'START' and 'START'+1.
* 2. "INC.W CNT,START" adds the value of 'CNT' to the contents
* of locations 'START' and 'START'+1.
* 3. "INC.W #,5,START" adds five to the contents of locations
* 'START' and 'START'+1.
*
* Register Usage:
* CC = reflects value incremented (Z-bit only).
* All other registers preserved.
*
* Notes:
* 1. <address> may be direct or extended!
* 2. This macro essentially performs an "ADD n" function.
*
INC.W MACR
IFEQ NARG-1
IFEQ (\0)!.$FF00
INC (\0)+1
BNE \.0
INC \0
\.0 EQU *
MEXIT
ENDC
IFNE (\0)!.$FF00
STA TEMPA$
LDA (\0)+1
ADD #1
STA (\0)+1
LDA \0
ADC #0
STA \0
ORA (\0)+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
IFEQ NARG-2
STA TEMPA$
LDA (\1)+1
ADD (\0)+1
STA (\1)+1
LDA \1
ADC \0
STA \1
ORA (\1)+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
IFEQ NARG-3
IFC '\0','#'
STA TEMPA$
LDA (\2)+1
ADD #(\1)!.$FF
STA (\2)+1
LDA \2
ADC #(\1)!>8
STA \2
ORA (\2)+1
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* MOV.B = move byte
* MOV.B [#,]<byte>,<address>
*
* where:
* <byte> = byte value to move to the <address> location, using
* immediate ("#," present) or absolute addressing ("#,"
* not present).
*
* Examples:
* 1. "MOV.B CNT,TMP" puts the contents of location 'CNT'
* into location 'TMP'.
* 2. "MOV.B #,5,START" puts 5 into location 'START'.
*
* Register Usage:
* CC = reflects value moved.
* All other registers preserved.
*
MOV.B MACR
IFEQ NARG-2
STA TEMPA$
LDA \0
STA \1
IFEQ (\1)!.$FF00
LDA TEMPA$
TST \1
MEXIT
ENDC
IFNE (\1)!.$FF00
IFEQ (\0)!.$FF00
LDA TEMPA$
TST \0
MEXIT
ENDC
IFNE (\0)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
IFEQ NARG-3
IFC '\0','#'
IFEQ (\2)!.$FF00
IFEQ \1
CLR \2
MEXIT
ENDC
ENDC
STA TEMPA$
IFEQ \1
CLRA
ENDC
IFNE \1
LDA #\1
ENDC
STA \2
IFEQ (\2)!.$FF00
LDA TEMPA$
TST \2
MEXIT
ENDC
IFNE (\2)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* MOV.W = move word
* MOV.W [#,]<word>,<address>
*
* where:
* <word> = word (16-bit) value to move to the <address> and
* <address>+1 locations, using immediate ("#," present)
* or absolute addressing ("#," not present).
*
* Examples:
* 1. "MOV.W #,5,START" puts $0005 into location 'START' and
* 'START'+1.
* 2. "MOV.W #,CNT,TMP" puts the value of symbol 'CNT' into
* locations 'TMP' and 'TMP'+1.
* 3. "MOV.W CNT,TMP" copies the contents of location 'CNT'
* and 'CNT'+1 into locations 'TMP' and
* 'TMP'+1.
*
* Register Usage:
* CC = reflects MS half of value moved.
* All other registers preserved.
*
MOV.W MACR
IFEQ NARG-2
STA TEMPA$
LDA (\0)+1
STA (\1)+1
LDA \0
STA \1
IFEQ (\1)!.$FF00
LDA TEMPA$
TST \1
MEXIT
ENDC
IFNE (\1)!.$FF00
IFEQ (\0)!.$FF00
LDA TEMPA$
TST \0
MEXIT
ENDC
IFNE (\0)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
IFEQ NARG-3
IFC '\0','#'
IFEQ ((\2)+1)!.$FF00
IFEQ \1
CLR \2
CLR \2+1
MEXIT
ENDC
ENDC
STA TEMPA$
IFEQ (\1)!.$00FF
CLRA
ENDC
IFNE (\1)!.$00FF
LDA #(\1)!.$00FF
ENDC
STA (\2)+1
IFEQ (\1)!>8
IFNE (\1)!.$00FF
CLRA
ENDC
ENDC
IFNE (\1)!>8
LDA #(\1)!>8
ENDC
STA \2
IFEQ (\2)!.$FF00
LDA TEMPA$
TST \2
MEXIT
ENDC
IFNE (\2)!.$FF00
STA TESTA$
LDA TEMPA$
TST TESTA$
MEXIT
ENDC
ENDC
ENDC
FAIL Macro syntax error detected!
ENDM
**************************************************************************
* MOVE = move block of memory
* MOVE [#],<source>,[#],<destination>,[#],<length>
*
* where:
* <source> is the address of the source memory block.
* <destination> is the address of the destination block.
* <length> is the length of the block to move, in bytes.
* Maximum of 65,536 bytes can be moved.
* # is optional character to denote immediate
* addressing for the next parameter
* Examples:
* 1. "MOVE #,ROM,#,RAM,#,CNT moves the block of memory starting at
* location 'ROM' for 'CNT' bytes, to
* location 'RAM'.
* 2. "MOVE #,ABC,#,XYZ,,CNT moves the block of memory starting at
* location 'ABC' for the number of bytes
* in locations 'CNT' and 'CNT'+1, to
* location 'XYZ'.
*
* Register Usage:
* CC = unknown.
* All other registers preserved.
*
* Subr. used:
* LDAXREG, STAXREG
*
* Macros used:
* None, because this macro was written to be as efficient as
* possible.
*
* Notes:
* 1. If all immediate addressing operands (#) and the move count is
* <= 256, then a special 'short form' is generated which DOES NOT
* contain any subroutine calls!
* 2. Depending on the exact parameters passed, not all registers,
* subroutines and/or macros may be used.
* 3. This macro takes advantage of the fact that there are in fact
* two XREGs, one for LOAD (XREG1$) and one for STORE (XREG2$).
* 4. The INCXR macro cannot be used here, because it assumes that
* XREG1$ = XREG2$.
*-------------------------------------------------------------------------
MOVE MACR
IFNE NARG-6
FAIL ** 'move' macro requires six arguments!
ENDC
IFC '\4','#' ! If all immediate operands (#) and move
IFC '\2','#' ! count <=256, use short form!
IFC '\0','#'
IFLE \5-256 ! No subr. calls!
STA TEMPA$
STX TEMPX$
LDX #(\5)
\.0 LDA (\1)-1,x
STA (\3)-1,x
DEX
BNE \.0
LDA TEMPA$
LDX TEMPX$
MEXIT
ENDC
ENDC
ENDC
ENDC
STA TEMPA$
STX TEMPX$
LDA XREG1$
STA TEMPXR$
LDA XREG1$+1
STA TEMPXR$+1
IFC '\0','#' ! immediate type 'from' address?
LDA #(\1)!.$FF
STA XREG1$+1 ! Set XREG1$ = 'from' address
LDA #(\1)!>8
STA XREG1$
ENDC
IFNC '\0','#' ! not immediate type 'from' address?
LDA (\1)+1
STA XREG1$+1 ! Set XREG1$ = 'from' address
LDA (\1)
STA XREG1$
ENDC
IFC '\2','#' ! immediate type 'to' address?
LDA #(\3)!.$FF
STA XREG2$+1 ! Set XREG2$ = 'to' address
LDA #(\3)!>8
STA XREG2$
ENDC
IFNC '\2','#' ! not immediate type 'to' address?
LDA (\3)+1
STA XREG2$+1 ! Set XREG2$ = 'to' address
LDA (\3)
STA XREG2$
ENDC
IFC '\4','#' ! immediate type length?
IFLE \5-256 ! yes: 8-bit size= use X reg.
LDX #(\5)
\.0 JSR LDAXREG
JSR STAXREG
IFEQ XREG1$!.$FF00
INC XREG1$+1
BNE \.1
INC XREG1$
\.1 INC XREG2$+1
BNE \.2
INC XREG2$
\.2 EQU *
ENDC
IFNE XREG1$!.$FF00
LDA XREG1$+1
ADD #1
STA XREG1$+1
LDA XREG1$
ADC #0
STA XREG1$
LDA XREG2$+1
ADD #1
STA XREG2$+1
LDA XREG2$
ADC #0
STA XREG2$
ENDC
DEX
BNE \.0
LDA TEMPXR$
STA XREG1$
STA XREG2$
LDA TEMPXR$+1
STA XREG1$+1
STA XREG2$+1
LDA TEMPA$
LDX TEMPX$
MEXIT
ENDC
*
IFGT \5-256 ! no: 16-bit size= use 'length'
LDA #(\5)!.$00FF
STA LENGTH$+1
LDA #(\5)!>8
STA LENGTH$
\.0 JSR LDAXREG
JSR STAXREG
IFEQ XREG1$!.$FF00
INC XREG1$+1
BNE \.1
INC XREG1$
\.1 INC XREG2$+1
BNE \.2
INC XREG2$
\.2 EQU *
ENDC
IFNE XREG1$!.$FF00
LDA XREG1$+1
ADD #1
STA XREG1$+1
LDA XREG1$
ADC #0
STA XREG1$
LDA XREG2$+1
ADD #1
STA XREG2$+1
LDA XREG2$
ADC #0
STA XREG2$
ENDC
LDA LENGTH$+1
SUB #1
STA LENGTH$+1
LDA LENGTH$
SBC #0
STA LENGTH$
ORA LENGTH$+1
BNE \.0
LDA TEMPXR$
STA XREG1$
STA XREG2$
LDA TEMPXR$+1
STA XREG1$+1
STA XREG2$+1
LDA TEMPA$
LDX TEMPX$
MEXIT
ENDC
ENDC
IFNC '\4','#' ! nonimmediate type length
LDA (\5)!.$00FF
STA LENGTH$+1
LDA (\5)!>8
STA LENGTH$
\.0 JSR LDAXREG
JSR STAXREG
IFEQ XREG1$!.$FF00
INC XREG1$+1
BNE \.1
INC XREG1$
\.1 INC XREG2$+1
BNE \.2
INC XREG2$
\.2 EQU *
ENDC
IFNE XREG1$!.$FF00
LDA XREG1$+1
ADD #1
STA XREG1$+1
LDA XREG1$
ADC #0
STA XREG1$
LDA XREG2$+1
ADD #1
STA XREG2$+1
LDA XREG2$
ADC #0
STA XREG2$
ENDC
LDA LENGTH$+1
SUB #1
STA LENGTH$+1
LDA LENGTH$
SBC #0
STA LENGTH$
ORA LENGTH$+1
BNE \.0
LDA TEMPXR$
STA XREG1$
STA XREG2$
LDA TEMPXR$+1
STA XREG1$+1
STA XREG2$+1
LDA TEMPA$
LDX TEMPX$
MEXIT
ENDC
FAIL Macro syntax error detected!
ENDM
OPT L
RAMSBR$ EQU * Start of RAM based subroutines!
**************************************************************************
** The following RAM subroutines MUST BE INITIALIZED from ROM upon **
** startup (from 'RAMSBR$' for 'RAMSZ$' number of bytes). If changes **
** are to be made to the RAM subroutines, make them here. Then copy **
** the source below to the ROM area and insert a '.' in front of all **
** the labels (leading '.' will be used to denote ROM). This has **
** already been done for you in the RAMSBR.INI file. Just include **
** this file into your ROM data area and add the following line in **
** your RESET routine to initialize the RAM subroutines from the ROM. **
** MOVE #,.RAMSBR,#,RAMSBR,#,RAMSZ$ **
** It is more efficient if the RAM subroutines are placed in DIRECT **
** addressing memory, i.e., $0000-$00FF, but it is not required. **
**************************************************************************
*-- start of RAM subroutines --------------------------------------------*
**************************************************************************
* LDAXREG = load A via XREG subr.
*
* Register Usage:
* CC = reflects value loaded.
* All other registers preserved.
*
* NOTE:
* 1. Instruction modified code here must be located in RAM!
*
LDAXREG EQU *
LDA 0-0+$FFFF
XREG1$ EQU *-2 Pseudo XREG #1
RTS
**************************************************************************
* STAXREG = store A via XREG subr.
*
* Register Usage:
* CC = reflects value stored.
* All other registers preserved.
*
* NOTE:
* 1. Instruction modified code here must be located in RAM!
*
STAXREG EQU *
STA 0-0+$FFFF
XREG2$ EQU *-2 Pseudo XREG #2
RTS
**************************************************************************
* LDAYREG = load A via YREG subr.
*
* Register Usage:
* CC = reflects value loaded.
* All other registers preserved.
*
* NOTE:
* 1. Instruction modified code here must be located in RAM!
*
LDAYREG EQU *
LDA 0-0+$FFFF
YREG1$ EQU *-2 Pseudo YREG #1
RTS
**************************************************************************
* STAYREG = store A via YREG subr.
*
* Register Usage:
* CC = reflects value stored.
* All other registers preserved.
*
* NOTE:
* 1. Instruction modified code here must be located in RAM!
*
STAYREG EQU *
STA 0-0+$FFFF
YREG2$ EQU *-2 Pseudo YREG #2
RTS
*-- end of RAM subroutines ----------------------------------------------*
RAMSZ$ EQU *-RAMSBR$ Size of ram subroutines (in bytes).
ORG LO$MEM
* NOTE: TEMPA$ and TESTA$ must always be in low memory $0000-00FF.
TEMPA$ RMB 1 Temporary storage for A accumulator.
TEMPX$ RMB 1 Temporary storage for X register.
TEMPXR$ RMB 2 Temporary storage for XREG register.
TESTA$ RMB 1 Temporary operand storage for setting CC bits.
LENGTH$ RMB 2 Temporary operand length.
**************************************************************************